An integrated circuit (IC) device may contain field effect transistors (FET). One such type of FET is a metal-oxide semiconductor FET, or MOSFET. MOSFETs have been scaled to smaller sizes to provide more room, and performance in an IC, thereby providing greater functionality in the IC.
One type of MOSFET which has been developed to improve performance is a finFET. A finFET is a MOSFET in which a portion of the silicon has been etched into a thin, “fin”-like shape. That is, a narrow channel of silicon is formed on a wafer, such as a silicon oxide insulating (SOI) wafer. A gate electrode is applied to the “fin” such that it wraps around on two or more sides. This results in a various number gate devices. For example, a gate electrode wrapped around three sides of the fin is a tri-gate device.
FIG. 1 illustrates a top view of a finFET 100 located on a wafer 110, such as a silicon oxide insulator (SOI) wafer. The finFET 100 includes a source 120, a drain 130 and a channel, or “fin,” 140. As seen, the fin 140 is relatively thinner than either of the source 120 and the drain 130. The source 120, drain 130, and fin 140 are made of silicon and are patterned on the SOI wafer 110 using known pattern techniques. A gate electrode 150 is placed over the fin channel to complete the finFET.
Tri-gate type finFETs, such as the finFET 100, generally require a thin gate oxide for the top surface of the channel of the fin. Such a thin gate oxide provides improved gate control and current drive on the top channel.
Conventional finFET devices use an oxide hard mask to prevent silicon consumption during the etching of the gate stack (that is, the fin 140), especially silicon consumption at the source drain extension region 140 of the finFET. However, silicon consumption still occurs, and may be particularly problematic for the thin gate oxides of the fin, due to the thinness of the layer, and the fact that the gate electrode material and the fin are the same material.
FIG. 2 illustrates a side view of a portion of the finFET 100, showing the gate 150 and the fin 140. However, as the top gate oxide is thin, silicon consumption in fin 140 during the gate stack etching process may cause problems with the performance of the finFET. This silicon consumption is illustrated at edges 145 of fin 140.